Zilog Z80180 - Manual (Page 296)

Z8018x
Family MPU User Manual
280
UM005003-0703
INT0 Mode 2
MC1 T1T2TW
TWT3 Next
Op Code
Address (PC) Vector 1 1 1 0 0 1 0
MC2 Ti * Z 1 1 1 1 1 1 1
MC3 T1T2T3 SP-1 PCH 1 0 0 1 1 1
MC4 T1T2T3 SP-2 PCL 1 0 0 1 1 1 1
MC5 T1T2T3 I, Vector DATA 0 1 0 1 1 1 1
MC6 T1T2T3
T1T2,TW I, Vector+1 DATA 0 1 0 1 1 1 1
INT1
INT2
Internal
Interrupts
MC1 T1T2,TW
TWT3 Next
Op Code
Address (PC) 1 1 1 1 1 1 0
MC2 Ti * Z 1 1 1 1 1 1 1
MC3 T1T2T3 SP-1 PCH 1 0 0 1 1 1 1
MC4 T1T2T3 SP-2 PCL 1 0 0 1 1 1 1
MC5 T1T2T3 I, Vector DATA 0 1 0 1 1 1 1
MC6 T1T2T3 I, Vector+1 DATA 0 1 0 1 1 1 1
Table 52. Interrupts (Continued)
Instruction
Machine
Cycle
States Address Data RD WR MREQ IORQ M1 HALT ST