Zilog Z80180 - Manual (Page 317)

Z8018x
Family MPU User Manual
UM005003-0703
301
DMA/WAIT Control
Register: DCNTL 3 2
Table 57. Internal I/O Registers (Continued)
Register Mnemonics Address Remarks
R/W R/W R/W R/W R/W R/W R/W R/W
1 1 1 1 0 0 0
MWI1 MWI0 IWI1 DMS0 DIMA1 DIMA0 IWI0
0
bit
during RESET
R/W
DMS1
The number of
0 0
MWI1,0
DMA Ch 1
I/O Memory
I/O Wait Insertion
Memory Wait Insertion
0
1
0 1
1 0
1 1
Mode Select
wait states
2
3
The number of
0 0
IWI1,0
0
2
0 1
1 0
1 1
wait states
3
4
1
DMSi
Edge sense
0
Sense
Level sense
0 0
DIM1,0
M ®I/O
0 1
1 0
1 1
Transfer Mode
M ®I/O
I/O ®M
I/O ®M
MAR1+1
Address Increment/Decrement
MAR1-1
IAR1 fixed
IAR1 fixed
IAR1 fixed
IAR1 fixed
MAR1+1
MAR1-1
DREQi Select, i=1,0