Zilog Z80180 - Manual (Page 148)

Z8018x
Family MPU User Manual
UM005003-0703
133
The external ASCI channel 0 data clock pins are multiplexed with DMA
control lines (CKA0/DREQ and CKA1/TEND0). During RESET, these
5 CTS/PS R/W Clear to Send/Prescale — When read, CTS /PS reflects
the state of the external CTS input. If the CTS input pin
is High, CTS /PS is read as 1. When the CTS input pin is
High, the TDRE bit is inhibited (that is, held at 0). For
channel 1, the
CTS 1 input is multiplexed with RXS pin
(Clocked Serial Receive Data). Thus, CTS /PS is only
valid when read if the channel 1 CTS1E bit is 1 and the
CST1 input pin function is selected. The read data of
CTS /PS is not affected by RESET.
When written, CT /PS specifies the baud rate generator
prescale factor. If
CTS /PS is set to 1, the system clock is
prescaled by 30 while if CTS /PS is cleared to 0, the
system clock is prescaled by 10.CTS/PS is cleared to 0
during RESET.
4 PEO R/W Parity Even Odd — PE0 selects even or odd parity. PE0
does not affect the enabling/disabling of parity (MOD1
bit of CNTLA). If PE0 is cleared to 0, even parity is
selected. If PE0 is set to 1, odd parity is selected.PE0 is
cleared to 0 during RESET.
3 DR R/W Divide Ratio — DR specifies the divider used to obtain
baud rate from the data sampling clock If DR is reset to 0,
divide by 16 is used, while if DR is set to 1, divide by 64
is used. DR is cleared to 0 during RESET.
2 – 0 SS2 – 0 R/W Source/Speed Select — Specifies the data clock source
(internal or external) and baud rate prescale factor. SS2,
SS1, and SS0 are all set to 1 during RESET. Table 18
describes the divide ratio corresponding to SS2, SS1 and
SS0
Bit
Position Bit/Field R/W
Value Description