Dma/wait control register (dcntl) – Zilog Z80180 User Manual
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Z8018x
Family MPU User Manual
100
UM005003-0703
DMA/WAIT Control Register (DCNTL)
DCNTL controls the insertion of Wait States into DMAC (and CPU)
accesses of memory or I/O Also, the DMA request mode for each DREQ
DREQ0 and DREQ1) input is defined as level or edge sense. DCNTL
also sets the DMA transfer mode for channel 1, which is limited to
memory to/from I/O transfers.
1
1
0
0
Memory
to
I/O
SAR0+1, DAR0 fixed
1
1
0
1
Memory
to
I/O
SAR0-1, DAR0 fixed
1
1
1
0
Reserved
1
1
1
1
Reserved
Note: *: includes memory mapped I/O.
Table 14. Transfer Mode Combinations
DM1 DM0 SM1 SM0 Transfer Mode
Increment/Decrement