Cpu operation and dma operation dreq0, Is programmed for edge-sense, Figure 49. tend0 output timing diagram – Zilog Z80180 User Manual

Page 123: Dma transfer (reference figure 49)

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Cpu operation and dma operation dreq0, Is programmed for edge-sense, Figure 49. tend0 output timing diagram | Dma transfer (reference figure 49) | Zilog Z80180 User Manual | Page 123 / 326

This manual is related to the following products:

Z80181 Z80182 Z80195 Z8L180 Z8L182 Z8S180