Digi NS9215 - Manual (Page 86)

W O R K I N G W I T H T H E C P U
R0: ID code and cache type status registers
86 Hardware Reference NS9215
The B bit is set to 0 at reset if the BIGENDINIT signal is low, and set to 1 if the
BIGENDINIT signal is high.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R 0 : I D c o d e a n d c a c h e t y p e s t a t u s r e g i s t e r s
Register R0 access the ID register, and cache type register. Reading from R0 returns
the device ID, and the cache type, depending on the
opcode_2 value:
The CRm field SHOULD BE ZERO when reading from these registers. This table shows
the instructions you can use to read register R0.
Writing to register R0 is UNPREDICTABLE .
R0: ID code
R0: ID code is a read-only register that returns the 32-bit device ID code. You can
access the ID code register by reading CP15 register R0 with the
opcode_2 field set to
any value other than 1 or 2. Note this example:
MRC p15, 0, Rd, c0, c0, {0, 3-7}; returns ID
This is the contents of the ID code register.
R0: Cache type
register
R0: Cache type is a read-only register that contains information about the size and
architecture of the instruction cache (ICache) and data cache (DCache) enabling
operating systems to establish how to perform operations such as cache cleaning
and lockdown. See “Cache features” on page 127 for more information about
cache.
opcode_2=0 ID value
opcode_2=1 instruction and data cache type
Function Instruction
Read ID code MRC p15,0,Rd,c0,c0,{0, 3-7}
Read cache type MRC p15,0,Rd,c0,c0,1
Bits Function Value
[31:24] ASCII code of implementer trademark 0x41
[23:20] Specification revision 0x0
[19:16] Architecture (ARMv5TEJ) 0x6
[15:4] Part number 0x926
[3:0] Layout revision 0x0