Tx error buffer descriptor pointer register – Digi NS9215 User Manual
Page 321
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E T H E R N E T C O M M U N I C A T I O N M O D U L E
Transmit Recover Buffer Descriptor Pointer register
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321
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T r a n s m i t R e c o v e r B u f f e r D e s c r i p t o r P o i n t e r r e g i s t e r
Address: A060 0A1C
Register
Register bit
assignment
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T X E r r o r B u f f e r D e s c r i p t o r P o i n t e r r e g i s t e r
Address: A060 0A20
Register
Reserved
TXRPTR
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
Bits
Access
Mnemonic
Reset
Description
D31:08
N/A
Reserved
N/A
N/A
D07:00
R/W
TXRPTR
0x00
Contains a pointer to a buffer descriptor in the TX buffer
descriptor RAM.
Note:
This pointer is the 8-bit physical address of the
TX buffer descriptor RAM, and points to the
first location of the four-location buffer
descriptor. The byte offset of this buffer
descriptor can be calculated by multiplying this
value by 4.
This is the buffer descriptor at which the
TX_WR
logic
resumes processing when TCLER is toggled from low to
high in Ethernet General Control Register #2.
Reserved
TXERBD
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved