Digi NS9215 - Manual (Page 397)

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S E R I A L C O N T R O L M O D U L E : U A R T
Interrupt Status register
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D11 R/W1TC MATCH3 0 Character match3
Indicates that a receive character match has occurred
against the Receive Match Register 3.
D10 R/W1TC MATCH2 0 Character match2
Indicates that a receive character match has occurred
against the Receive Match Register 2.
D09 R/W1TC MATCH1 0 Character match1
Indicates that a receive character match has occurred
against the Receive Match Register 1.
D08 R/W1TC MATCH0 0 Character match0
Indicates that a receive character match has occurred
against the Receive Match register 0.
D07 R/W1TC DSR 0 Data set ready
Indicates that a state change has occurred on input signal
DSR.
D06 R/W1TC DCD 0 Data carrier detect
Indicates that a state change has occurred in input signal
DCD.
D05 R/W1TC CTS 0 Clear to send
Indicates that a state change has occurred on input signal
CTS.
D04 R/W1TC RI 0 Ring indicator
Indicates that a state change has occurred on input signal
RI.
D03 R/W1TC TBC 0 Transmit buffer close
Indicates that transmission of the last byte in a transmit
buffer has completed.
D02 R/W1TC RBC 0 Receive buffer close
Indicates that a UART receive buffer close condition has
occurred. These are UART receive buffer close events:
1
Receive character match
2 Receive character gap timeout
3 Receive line break
4 Receive framing error
5 Receive parity error
Bits Access Mnemonic Reset Description