Memory bus interface – Digi NS9215 User Manual
Page 28
P I N O U T ( 2 6 5 )
Memory bus interface
28
Hardware Reference NS9215
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M e m o r y b u s i n t e r f a c e
Pin
Signal
U/D
I/O
OD
Description
B9
clk_out[0]
O
4
SDRAM bus clock
A15
clk_out[1]
O
4
SDRAM bus clock
P12
addr[27] / gpio_a[3]
a
U
I/O
4
Address bus, Endian
T14
addr[26] / gpio_a[2]
U
I/O
4
Address bus, SPI boot
U15
addr[25] / gpio_a[1]
U
I/O
4
Address bus
R12
addr[24] / gpio_a[0]
U
I/O
4
Address bus, Boot width [1]
T13
addr[23]
U
I/O
4
Address bus, Boot width [0]
U14
addr[22]
O
4
Address bus
T12
addr[21]
O
4
Address bus
U13
addr[20]
O
4
Address bus,
R11
addr[19]
U
I/O
4
Address bus, GENID 10
T11
addr[18]
U
I/O
4
Address bus, GENID 9
U12
addr[17]
U
I/O
4
Address bus, GENID 8
T10
addr[16]
U
I/O
4
Address bus, GENID 7
R9
addr[15]
U
I/O
4
Address bus, GENID 6
U11
addr[14]
U
I/O
4
Address bus, GENID 5
U10
addr[13]
U
I/O
4
Address bus, GENID 4
T9
addr[12]
U
I/O
4
Address bus, GENID 3
U9
addr[11]
U
I/O
4
Address bus, GENID 2
U8
addr[10]
U
I/O
4
Address bus, GENID 1
T8
addr[9]
U
I/O
4
Address bus, GENID 0
U7
addr[8]
U
I/O
4
Address bus
T7
addr[7]
U
I/O
4
Address bus, PLL bypass
U6
addr[6]
U
I/O
4
Address bus, PLL OD [1]
T6
addr[5]
U
I/O
4
Address bus, PLL OD [0]
U5
addr[4]
U
I/O
4
Address bus, PLL NR[4]
M2
addr[3]
U
I/O
4
Address bus, PLL NR[3]
N1
addr[2]
U
I/O
4
Address bus, PLL NR[2]
L2
addr[1]
U
I/O
4
Address bus, PLL NR[1]