Dynamic memory auto refresh period register – Digi NS9215 User Manual
Page 243
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M E M O R Y C O N T R O L L E R
Dynamic Memory Active to Active Command Period register
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243
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D y n a m i c M e m o r y A c t i v e t o A c t i v e C o m m a n d P e r i o d r e g i s t e r
Address: A070 0048
The Dynamic Memory Active to Active Command Period register allows you to
program the active to active command period, t
RC
. It is recommended that this
register be modified during system initialization, or when there are no current or
outstanding transactions. Wait until the memory controller is idle, then enter low-
power or disabled mode. This value normally is found in SDRAM datasheets as t
RC
.
Note:
The Dynamic Memory Active to Active Command period register is used for all
four dynamic memory chip selects. The worst case value for all chip selects
must be programmed.
Register
Register bit
assignment
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D y n a m i c M e m o r y A u t o R e f r e s h P e r i o d r e g i s t e r
Address: A070 004C
The Dynamic Memory Auto Refresh Period register allows you to program the auto-
refresh period and the auto-refresh to active command period, t
RFC
. It is
recommended that this register be modified during initialization, or when there are
no current or outstanding transactions. Wait until the memory controller is idle,
then enter low-power or disabled mode. This value normally is found in SDRAM
datasheets as t
RFC
or t
RC
.
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
Reserved
RC
Bits
Access
Mnemonic
Description
D31:05
N/A
Reserved
N/A (do not modify)
D04:00
R/W
RC
Active to active command period (t
RC
)
0x0–0x1E
n+1 clock cycles, where the delay is in
clk_out
cycles.
0x1F
32 clock cycles (reset value on
reset_n
)