Spi timing – Digi NS9215 User Manual
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T I M I N G
Memory Timing
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SPI Timing
All AC characteristics are measured with 10pF, unless otherwise noted.
The next table describes the values shown in the LCD timing diagrams.
Parm
Description
Min
Max
Unit
Mod
es
Not
es
SPI master parameters
SPO
SPI enable low setup to first SPI CLK out
rising
3*T
BCLK
-10
ns
0,3
1,3
SP1
SPI enable low setup to first SPI CLK out
falling
3*T
BCLK
-10
ns
1,2
1,3
SP3
SPI data in setup to SPI CLK out rising
30
ns
0,3
SP4
SPI data in hold from SPI CLK out rising
0
ns
0,3
SP5
SPI data in setup to SPI CLK out falling
30
ns
1,2
SP6
SPI data in hold from SPI CLK out falling 0
ns
1,2
SP7
SPI CLK out falling to SPI data out valid
10
ns
0,3
6
SP8
SPI CLK out rising to SPI data out valid
10
ns
1,2
6
SP9
SPI enable low hold from last SPI CLK out
falling
3*T
BCLK
-10
+2
ns
0,3
1,3
SP1O
SPI enable low hold from last SPI CLK out
rising
3*T
BCLK
-10
ns
1,2
1,3
SP11
SPI CLK out high time
SP13*45%
SPI3*55%
ns
0,1,2,
3
4
SP12
SPI CLK out low time
-SP13*45%
SPI3*55%
ns
0,1,2,
3
4
SP13
SPI CLK out period
T
BCLK
*6
ns
0,1,2,
3
3
SPI slave parameters
SP14
SPI enable low setup to first SPI CLK in
rising
30
ns
0,3
1
SP15
SPI enable low setup to first SPI CLK in
falling
30
ns
1,2
1
SP16
SPI data in setup to SPI CLK in rising
0
ns
0,3
SP17
SPI data in hold from SPI CLK in rising
60
ns
0,3
SP18
SPI data in setup to SPI CLK in falling
0
ns
1,2
SP19
SPI data in hold from SPI CLK in falling
60
ns
1,2
SP20
SPI CLK in falling to SPI data out valid
20
70
ns
0,3
6
SP21
SPI CLK in rising to SPI data out valid
20
70
ns
1,2
6