Dynamic memory write recovery time register, Register bit assignment, Or t – Digi NS9215 User Manual
Page 242
M E M O R Y C O N T R O L L E R
Dynamic Memory Write Recovery Time register
242
Hardware Reference NS9215
Register bit
assignment
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D y n a m i c M e m o r y W r i t e R e c o v e r y T i m e r e g i s t e r
Address: A070 0044
The Dynamic Memory Write Recovery Time register allows you to program the write
recovery time, t
WR
. It is recommended that this register be modified during system
initialization, or when there are no current or outstanding transactions. Wait until
the memory controller is idle, then enter low-power or disabled mode. This value
normally is found in SDRAM datasheets as t
WR
, t
DPL
, t
RWL
, or t
RDL
.
Note:
The Dynamic Memory Write Recovery Time register is used for all four
dynamic memory chip selects. The worst case value for all chip selects must
be programmed.
Register
Register bit
assignment
Bits
Access
Mnemonic
Description
D31:04
N/A
Reserved
N/A (do not modify)
D03:00
R/W
DAL
Data-in to active command (t
DAL
or t
APW
)
0x0–0xE
n+1 clock cycles, where the delay is in
clk_out
cycles.
0xF
15 clock cycles (reset value on
reset_n
)
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
Reserved
WR
Bits
Access
Mnemonic
Description
D31:04
N/A
Reserved
N/A (do not modify)
D03:00
R/W
WR
Write recovery time (t
WR
, t
DPL
, t
RWL
, or t
RDL
)
0x0–0xE
n+1 clock cycles, where the delay is in
clk_out
cycles.
0xF
16 clock cycles (reset value on
reset_n
)