Digi NS9215 - Manual (Page 497)

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T I M I N G
Memory Timing
www.digiembedded.com 497
Static RAM read
cycle with
configurable wait
states
WTRD = from 1 to 15
WOEN = from 0 to 15
If the PB field is set to 1, all four
byte_lane
signals will go low for 32-bit,
16-bit, and 8-bit read cycles.
If the PB field is set to 0, the
byte_lane
signal will always be high.
M 24 M 23
M 28 M 27
M 20 M 19
M1 8 M 17
M 26
M 25
N ote -1
N ote -1
N ote -1
clk_ ou t
d ata < 31: 0>
ad dr< 27: 0>
st_cs_ n<3: 0>
oe _n
byte _lan e<3: 0>