Digi NS9215 - Manual (Page 495)

. . . . .
T I M I N G
Memory Timing
www.digiembedded.com 495
static_rd_0wt.mif
Static RAM read
cycles with 0 wait
states
WTRD = 1
WOEN = 0
If the PB field is set to 1, all four byte_lane signals will go low for 32-bit, 16-
bit, and 8-bit read cycles.
If the PB field is set to 0, the byte_lane signal will always be high.
M 24 M 2 3
M 28 M 2 7
M 20 M 1 9
M 18 M 1 7
M 26
M2 5
S t ti R A M d l
c lk _ ou t
d ata < 31: 0>
ad dr < 27: 0>
s t_c s _ n< 3: 0>
oe _n
by te _lan e< 3: 0>