Module] direct mode rx status fifo – Digi NS9215 User Manual
Page 378
I / O H U B M O D U L E
[Module] Direct Mode RX Status FIFO
378
Hardware Reference NS9215
31 March 2008
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[ M o d u l e ] D i r e c t M o d e R X S t a t u s F I F O
Addresses: 9000_0010 / 9000_8010 / 9001_0010 / 9001_8010 / 9002_0010 /
9002_8010 / 9003_0010 / 9003_8010
The Direct Mode RX Status FIFO register is used when in direct mode of operation,
to determine the status of the receive FIFO.
This register must be read before each read to the RX Data FIFO register.
The RX Data FIFO register must be read after each read to this register, even if
the BYTE field is 0.
Register
D26
R/W
RXFOFIE
0x0
Enable the RXFOFIP interrupt.
D25
R/W
RXFSRIE
0x0
Enable the RXFSRIP interrupt.
D24
R/W
RXNCIE
0x0
Enable the RXNCIP interrupt.
D23
R/W
RXECIE
0x0
Enable the RXECIP interrupt.
D22
R/W
RXNRIE
0x0
Enable the RXNRIP interrupt.
D21
R/W
RXCAIE
0x0
Enable the RXCAIP interrupt.
D20
R/W
RXPCIE
0x0
Enable the RXPCIP interrupt.
D19
R
WSTAT
0x0
Debug field, indicating the W bit is set in the
current buffer descriptor.
D18
R
ISTAT
0x0
Debug field, indicating the I bit is set in the current
buffer descriptor.
D17
R
LSTAT
0x0
Debug field, indicating the L bit is set in the
current buffer descriptor.
D16
R
FSTAT
0x0
Debug field, indicating the F bit is set in the
current buffer descriptor.
D15:00
R
BLENSTAT
0x0
Debug field, indicating the current byte count.
Bit(s)
Access
Mnemonic
Reset
Description
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
PSTAT
Reserved
Reserved
BYTE
Reserved
FFL
AG