Ahb error detect status 2, The ahb error detect status 1 register records the – Digi NS9215 User Manual
Page 160
S Y S T E M C O N T R O L M O D U L E
AHB Error Detect Status 2
160
Hardware Reference NS9215
The AHB Error Detect Status 1 register records the
haddr[31:0]
value present when any
AHB error is found. Note that this value is not reset on powerup but is reset when
the AHB Error Interrupt Clear bit is set in the AHB Error Monitoring Configuration
register (*).
Register
Register bit
assignment
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A H B E r r o r D e t e c t S t a t u s 2
Address: A090 001C
The AHB Error Detect Status 2 register records AHB master and slave values present
when any AHB error is found. This register also records which error condition was
triggered. Note that this value is not reset on powerup but is reset when the AHB
Interrupt Clear bit is set in the AHB Error Monitoring Configuration register (*).
Register
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
EDSI
EDSI
Bits
Access
Mnemonic
Reset
Description
D31:00
*
EDS1
Not reset
The
haddr[31:0]
value recorded during a slave error
response.
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
HPR
Reserved
HBRST
IE
DE
ER
Reser
ved
Re
ser
ved
HSZ
HMSTR
H
W
R