Dynamic memory ras and cas delay 0-3 registers, Chip select and memory devices, Dynamic memory ras and cas delay 0–3 registers – Digi NS9215 User Manual
Page 250
M E M O R Y C O N T R O L L E R
Dynamic Memory RAS and CAS Delay 0–3 registers
250
Hardware Reference NS9215
Chip select and
memory devices
A chip select can be connected to a single memory device; in this situation, the chip
select data bus width is the same as the device width. As an alternative, the chip
select can be connected to a number of external devices. In this situation, the chip
select data bus width is the sum of the memory device databus widths.
Chip select and
memory devices:
Examples
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D y n a m i c M e m o r y R A S a n d C A S D e l a y 0 – 3 r e g i s t e r s
Address: A070 0104 / 0124 / 0144 / 0164
1
0
011
01
256 Mb (16Mx16), 4 banks, row length=13, column length=9
1
0
011
10
256 Mb (8Mx32), 4 banks, row length=13, column length=8
1
0
100
00
512 Mb (64Mx8), 4 banks, row length=13, column length=11
1
0
100
01
512 Mb (32Mx16), 4 banks, row length=13, column length=10
32-bit extended bus low-power SDRAM address mapping (bank, row, column)
1
1
000
00
16 Mb (2Mx8), 2 banks, row length=11, column length=9
1
1
000
01
16 Mb (1Mx16), 2 banks, row length=11, column length=8
1
1
001
00
64 Mb (8Mx8), 4 banks, row length=12, column length=9
1
1
001
01
64 MB (4Mx16), 4 banks, row length=12, column length=8
1
1
001
10
64 Mb (2Mx32), 4 banks, row length=11, column length=8
1
1
010
00
128 Mb (16Mx8), 4 banks, row length=12, column length=10
1
1
010
01
128 Mb (8Mx16), 4 banks, row length=12, column length=9
1
1
010
10
128 Mb (4Mx32), 4 banks, row length=12, column length=8
1
1
011
00
256 Mb (32Mx8), 4 banks, row length=13, column length=10
1
1
011
01
256 Mb (16Mx16), 4 banks, row length=13, column length=9
1
1
011 10
256 Mb (8Mx32), 4 banks, row length=13, column length=8
1
1
100
00
512 Mb (64Mx8), 4 banks, row length=13, column length=11
1
1
100
01
512 Mb (32Mx16), 4 banks, row length=13, column length=10
[14]
[12]
[11:9]
[8:7]
Description
For a chip select connected to
Select this mapping
32-bit wide memory device
32-bit wide address mapping
16-bit wide memory device
16-bit wide address mapping
4 x 8-bit wide memory devices
32-bit wide address mapping
2 x 8-bit memory devices
16-bit wide address mapping