Digi NS9215 - Manual (Page 372)

I / O H U B M O D U L E
[Module] Interrupt and FIFO Status register
372 Hardware Reference NS9215 31 March 2008
RTC register
address map
IO Hardware
Assist register
address map (0)
IO Hardware
Assist register
address map (1)
IO register
address map (0)
IO register
address map (1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
[ M o d u l e ] I n t e r r u p t a n d F I F O S t a t u s r e g i s t e r
Addresses: 9000_0000 / 9000_8000 / 9001_0000 / 9001_8000 / 9002_0000 /
9002_8000 / 9003_0000 / 9003_8000
The Interrupt and FIFO Status register allows software to determine the cause of
the current low speed peripheral interrupts and to clear the interrupt bit.
Note:
An access type of R/W* means that the processor must write 1 to clear the
value if the read value is 1. If the read value is 0, the write value must be 0.
Register Offset Description (31:00)
0x9006_0000 – 0x9006_00BF
0x9006_0000 – 0x9006_00FC RTC CSR Space
64-byte Battery Backed RAM
Register Offset Description (31:00)
0x9006_8000 – 0x9006_FFFF IO Hardware Assist CSR Space for Flexible I/O Module 0
Register Offset Description (31:00)
0x9007_0000 – 0x9007_7FFF IO Hardware Assist CSR Space for Flexible I/O Module 1
Register Offset Description (31:00)
0x9008_0000 – 0x9008_FFFF IO Space for Flexible I/O Module 0
Register Offset Description (31:00)
0x9009_0000 – 0x9009_FFFF IO Space for Flexible I/O Module 1