Module] direct mode tx data fifo – Digi NS9215 User Manual
Page 382
I / O H U B M O D U L E
[Module] Direct Mode TX Data FIFO
382
Hardware Reference NS9215
31 March 2008
Register bit
assignment
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
[ M o d u l e ] D i r e c t M o d e T X D a t a F I F O
Addresses: 9000_0028 / 9000_8028 / 9001_0028 / 9001_8028 / 9002_0028 /
9002_8028 / 9003_0028
The Direct Mode TX Data FIFO register is used when in direct mode of operation, to
write the TX data FIFO. The write can be 8-, 16-, or 32-bit.
Register
Bit(s)
Access
Mnemonic
Reset
Description
D31:28
R/W
TXTHRS
0xF
TX FIFO threshold
An interrupt is generated when the FIFO level
drops below this level.
D27
N/A
Reserved
N/A
N/A
D26
R/W
TXFUFIE
0x0
Enable the TXFUFIP interrupt.
D25
R/W
TXFSRIE
0x0
Enable the TXFSRIP interrupt.
D24
R/W
TXNCIE
0x0
Enable the NCIP interrupt.
D23
R/W
TXECIE
0x0
Enable the ECIP interrupt.
D22
R/W
TXNRIE
0x0
Enable the NRIP interrupt.
D21
R/W
TXCAIE
0x0
Enable the CAIP interrupt.
D20
N/A
Reserved
N/A
N/A
D19
R
WSTAT
0x0
Debug field, indicating the W bit is set in the
current buffer descriptor.
D18
R
ISTAT
0x0
Debug field, indicating the I bit is set in the current
buffer descriptor.
D17
R
LSTAT
0x0
Debug field, indicating the L bit is set in the
current buffer descriptor.
D16
R
FSTAT
0x0
Debug field, indicating the F bit is set in the
current buffer descriptor.
D15:00
R
BLENSTAT
0x0
Debug field, indicating the current byte count.
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
TXD
TXD