Digi NS9215 - Manual (Page 230)

M E M O R Y C O N T R O L L E R
Registers
230 Hardware Reference NS9215
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R e g i s t e r s
Register map
All configuration registers must be accessed as 32-bit words and as single accesses
only. Bursting is not allowed.
addr[15]
addr[16]
addr[17]
addr[18]
addr[19]
addr[20] BA
addr[21] BA0 BA0 BA0 BA0
addr[22] BA1 BA1 BA1 BA1
ap10 A10/AP A10/AP A10/AP A10/AP
data[31:16] D[15:0] D[15:0] D[15:0] D[15:0]
* A12 used only in 2 x 16M x 8 configurations
Signal 16M device
SDRAM
signal 64M device
SDRAM
signal 128M
device
SDRAM
signal 256M
device
SDRAM
signal 512M
device
SDRAM
signal
Address Register Description
A070 0000 Control register Control register
A070 0004 Status register Status register
A070 0008 Config register Configuration register
A070 0020 DynamicControl Dynamic Memory Control register
A070 0024 DynamicRefresh Dynamic Memory Refresh Timer
A070 0028 DynamicReadConfig Dynamic Memory Read Configuration register
A070 0030 DynamictRP Dynamic Memory Precharge Command Period (t
RP
)
A070 0034 DynamictRAS Dynamic Memory Active to Precharge Command
Period (t
RAS
)
A070 0038 DynamictSREX Dynamic Memory Self-Refresh Exit Time (t
SREX
)
A070 003C DynamictAPR Dynamic Memory Last Data Out to Active Time
(t
APR
)
A070 0040 DynamictDAL Dynamic Memory Data-in to Active Command Time
(t
DAL
or T
APW
)