Digi NS9215 - Manual (Page 358)

A E S D A T A E N C R Y P T I O N / D E C R Y P T I O N M O D U L E
AES DMA buffer descriptor
358 Hardware Reference NS9215
AES op code
Indicates the contents of the data buffer associated with this descriptor:
000 Non-AES memory-to-memory or external DMA mode
001 Key buffer
010 IV buffer
011 Nonce buffer (CCM mode only, 16 bytes fixed length)
100 Additional authentication data (CCM mode only)
101 Data to be encrypted or decrypted
WRAP (W) bit
The Wrap (W) bit, when set, tells the DMA controller that this is the last buffer
descriptor within the continuous list of descriptors. The next buffer descriptor is
found using the initial DMA channel buffer descriptor pointer. When the W bit is not
set, the next buffer descriptor is found using an offset of 0x10 from the current
buffer descriptor.
Interrupt (I) bit
The Interrupt bit, when set, tells the DMA controller to issue an interrupt to the CPU
when the buffer is closed due to a normal channel completion. The interrupt occurs
regardless of the normal completion interrupt enable configuration for the DMA
channel.
Last (L) bit
The Last bit, when set, tells the DMA controller that this buffer descriptor is the last
descriptor that completes an entire message frame. The DMA controller uses this bit
to assert the normal channel completion status when the byte count reaches zero.
Full (F) bit
The Full bit, when set, indicates that the buffer descriptor is valid and can be
processed by the DMA channel. The DMA channel clears this bit after completing the
transfer(s).
[5:4] Key size 00 128 bits
01 192 bits
10 256 bits
[6] Additional authentication data (CCM
mode only) 0 No additional data
1 Additional data used
[9:7] L-par (CCM mode only) N/A
[10] Reserved N/A
[13:11] M-par (CCM mode only) N/A
[15:14] Reserved N/A
Bits Used for Values