Digi NS9215 - Manual (Page 457)

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I 2 C M A S T E R / S L A V E I N T E R F A C E
Flow charts
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F l o w c h a r t s
Master module
(normal mode, 16-
bit)
Notes:
1
Writing
M_ADDR_REQ
is not required if the device address is not changed.
2
Read on a non-existing slave.
3
Do not wait for the slave to perform a
NO_ACK
.
4 STATUS_REG and RX_DATA_REG are read simultaneously.
host idle
write (optional)
M_ADDR_REG
write cmd
M_READ
wait irq
read
rx/status
wait irq
read
rx/status
M_RX_DATA
irq
M_ARBIT_LOST
irq
M_NO_ACK
irq
write cmd
M_STOP
wait irq
read status
M_CMD_ACK
irq
write cmd
M_WRITE
write
TX_DATA_REG
write cmd
M_NOP
write
TX_DATA_REG
wait irq
read status
M_TX_DATA
irq
write cmd
M_NOP
write cmd
M_STOP
4
4
2
3
1
write cmd
M_WRITE
write (optional)
M_ADDR_REG
write cmd
M_READ
1