Digi NS9215 - Manual (Page 371)

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I / O H U B M O D U L E
Control and status register address maps
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SPI register
address map
AD register
address map
Reserved
Registers 9004_0000 – 9004_7FFF and 9004_8000 – 9004_FFFF are reserved.
I
2
C register
address map
Reserved
Registers 9005_8000 – 9005_FFFF are reserved.
0x9002_8030 – 0x9002_8FFF Reserved
0x9002_9000 – 0x9002_FFFF UART D CSR Space
Register Offset Description (31:00)
Register Offset Description (31:00)
0x9003_0000 SPI Interrupt and FIFO Status
0x9003_0004 SPI DMA RX Control
0x9003_0008 SPI DMA RX Buffer Descriptor Pointer
0x9003_000C SPI DMA RX Interrupt Configuration register
0x9003_0010 SPI Direct Mode RX Status FIFO
0x9003_0014 SPI Direct Mode RX Data FIFO
0x9003_0018 SPI DMA TX Control
0x9003_001C SPI DMA TX Buffer Descriptor Pointer
0x9003_0020 SPI DMA TX Interrupt Configuration register
0x9003_0024 Reserved
0x9003_0028 SPI Direct Mode TX Data FIFO
0x9003_002C SPI Direct Mode TX Data Last FIFO
0x9003_0030 – 0x9003_0FFF Reserved
0x9003_1000 – 0x9003_7FFF SPI CSR Space
Register Offset Description (31:00)
0x9003_8000 – 0x9003_8FFF Reserved
0x9003_9000 – 0x9003_FFFF AD CSR Space
Register Offset Description (31:00)
0x9005_0000 – 0x9005_7FFF I 2 C CSR Space