External interrupt 0-3 control register, External interrupt 0–3 control register, Register register bit assignment – Digi NS9215 User Manual
Page 199
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S Y S T E M C O N T R O L M O D U L E
External Interrupt 0–3 Control register
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199
Register
Register bit
assignment
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E x t e r n a l I n t e r r u p t 0 – 3 C o n t r o l r e g i s t e r
Addresses: A090 0214 / 0218 / 021C / 0220
The External Interrupt Control registers control the behavior of external
interrupts 0–3.
Register
Register bit
assignment
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
GENID
Reserved
Bits
Access
Mnemonic
Reset
Description
D31:11
N/A
Reserved
N/A
N/A
D10:00
R
GENID
HW strap
addr[19:09]
General Purpose ID register
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
Reserved
STS
CLR
PLTY
LVEDG
Bits
Access
Mnemonic
Reset
Description
D31:04
N/A
Reserved
N/A
N/A
D03
R
STS
N/A
Status
Status of the external signal before edge detect or level
conversion.
D02
R/W
CLR
0x0
Clear
Write a 1, then a 0 to this bit to clear the interrupt
generated by the edge detect circuit.