Digi NS9215 - Manual (Page 499)

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T I M I N G
Memory Timing
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Static RAM write
cycle
WTWR = 0
WWEN = 0
During a 32-bit transfer, all four byte_lane signals will go low.
During a 16-bit transfer, two byte_lane signals will go low.
During an 8-bit transfer, only one byte_lane signal will go low.
Note:
If the PB field is set to 0, the byte_lane signals will function as write enable
signals and the we_n signal will always be high.
M 2 2 M 21
M 2 4 M 23
M 2 2 M 21
M 2 0 M 19
M 1 8 M 17
M 1 6 M 15
N ot e- 1
clk_ ou t
d ata < 31: 0>
ad dr < 27: 0>
st_cs_ n< 3: 0>
we _n
byte _lan e< 3: 0>
byte _lan e[ 3:0 ] a s WE *