Rx fifo ram, Offset+4 offset+8 offset+c – Digi NS9215 User Manual
Page 333
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E T H E R N E T C O M M U N I C A T I O N M O D U L E
RX FIFO RAM
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333
Offset+4
Offset+8
Offset+C
See “Transmit buffer descriptor format” on page 270, for more information about
the fields in Offset+C.
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R X F I F O R A M
Address: A060 2000 (512 locations)
The 2k Byte RX FIFO RAM can be used by the CPU as a scratch pad memory during
boot up. CPU access is enabled by setting the RXRAM bit in the Ethernet General
Control Register 1. This bit must be cleared before enabling the Ethernet receiver.
Register
Register bit
assignment
D31:11
R/W
Not used
D10:00
R/W
Buffer length
D31:00
R/W
Destination address (not used)
D31
R/W
W
Wrap
D30
R/W
I
Interrupt on buffer completion
D29
R/W
L
Last buffer on transmit frame
D28
R/W
F
Buffer full
D27:16
R/W
Reserved
N/A
D15:00
R/W
Status
Transmit status from MAC
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Scr Mem
Scr Mem
Bits
Access
Mnemonic
Reset
Description
D31:00
R/W
Scr Mem
0
CPU scratch pad memory