Module] dma tx buffer descriptor pointer, Module] tx interrupt configuration register – Digi NS9215 User Manual
Page 381
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I / O H U B M O D U L E
[Module] DMA TX Buffer Descriptor Pointer
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381
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[ M o d u l e ] D M A T X B u f f e r D e s c r i p t o r P o i n t e r
Addresses: 9000_001C / 9000_801C / 9001_001C / 9001_801C / 9002_001C /
9002_801C / 9003_001C
The DMA TX Buffer Descriptor Pointer is the address of the first buffer descriptor for
each DMA channel.
Register
Register bit
assignment
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[ M o d u l e ] T X I n t e r r u p t C o n f i g u r a t i o n r e g i s t e r
Addresses: 9000_0020 / 9000_8020 / 9001_0020 / 9001_8020 / 9002_0020 /
9002_8020 / 9003_0020
The TX Interrupt Configuration register allows system software to configure the
interrupt from the I/O hub module transmit channel.
Register
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
TXBDP
TXBDP
Bit(s)
Access
Mnemonic
Reset
Description
D31:00
R/W
TXBDP
0x0
The first buffer descriptor in the ring. Used when
the W bit is found, which indicates the last buffer
descriptor in the list.
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reser
ved
BLENSTAT
TXTHRS
TXFUFIETXFURIE TXNCIE TXECIE TXNRIE TXCAIE Reserved WSTAT ISTAT LSTA FSTAT