Register bit assignment, Or t – Digi NS9215 User Manual
Page 246
M E M O R Y C O N T R O L L E R
Dynamic Memory Load Mode register to Active Command Time register
246
Hardware Reference NS9215
Register bit
assignment
D y n a m i c M e m o r y L o a d M o d e r e g i s t e r t o A c t i v e C o m m a n d
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T i m e r e g i s t e r
Address: A070 0058
The Dynamic Memory Load Mode register to Active Command Time register allows
you to program the Load Mode register to active command time, t
MRD
. It is
recommended that this register be modified during system initialization, or when
there are no current or outstanding transactions. Wait until the memory controller
is idle, then enter low-power or disabled mode. This value normally is found in
SDRAM datasheets as t
MRD
or t
RSA
.
Note:
The Dynamic Memory Load Mode register to Active Command Time register is
used for all four chip selects. The worst case value for all chip selects must be
programmed.
Register
Register bit
assignment
Bits
Access
Mnemonic
Description
D31:04
N/A
Reserved
N/A (do not modify)
D03:00
R/W
RRD
Active Bank A to Active Bank B
0x0–0xE
n+1 clock cycles, where the delay is in
clk_out
cycles
0xF
16 clock cycles (reset on
reset_n
)
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
Reserved
MRD
Bits
Access
Mnemonic
Description
D31:045
N/A
Reserved
N/A (do not modify)
D03:00
R/W
MRD
Load mode register to Active Command Time
0x0–0xE
n+1 clock cycles, where the delay is in
clk_out
cycles
0xF
16 clock cycles (reset on
reset_n
)