Hdlc data register 3, Register register bit assignment – Digi NS9215 User Manual
Page 428
S E R I A L C O N T R O L M O D U L E : H D L C
HDLC Data register 3
428
Hardware Reference NS9215
Register
Register bit
assignment
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
H D L C D a t a r e g i s t e r 3
Address: 9002_9108
HDLC Data Register 3 writes the last byte of data of a frame after which the closing
flag is transmitted. This register is for debug purposes only.
Register
Register bit
assignment
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
HDATA
Reserved
Bits
Access
Mnemonic
Reset
Description
D31:08
N/A
Reserved
N/A
N/A
D07:00
R/W
HDATA
0
Read
Returns the contents of the receive buffer
Write Used for the last data byte in a frame, after which
the CRC and closing flag are transmitted
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
HDATA
Reserved
Bits
Access
Mnemonic
Reset
Description
D31:08
N/A
Reserved
N/A
N/A
D07:00
R/W
HDATA
0
Read
Returns the contents of the receive buffer
Write Used for the last data byte in a frame, after which
the closing flag is transmitted