Motorola DSP96002 User Manual

Page 97

MOTOROLA

DSP96002 USER’S MANUAL

7 - 11

7.3.1.3

PSR X Data Memory Port Select (X0-X7) Bits 16-23

The X Data Memory Port Select control bits (X0-X7) determine the assignment of the 8 X Data Memory seg-

ments to Port A or B. If the segment bit is cleared, the X Data Memory segment is assigned to Port A. If the

segment bit is set, the memory segment is assigned to Port B. The memory segment to control bit correla-

tion is shown in Figure 7-6. For example, if the X4 bit is set, then all memory traffic for addresses

X:$80000000 to X:$9FFFFFFF will go thorough Port B. During hardware reset, the X0-X7 bits are cleared.

7.3.1.4

PSR Reserved Bits (Bits 24-31)

These reserved bits read as zero and should be written with zero for future compatibility.

7.4

HOST INTERFACES

7.4.1 Introduction

The DSP96002 provides a Host MPU/DMA Interface for each of its ports. The Host MPU/DMA Interface

provides a 32-bit parallel port to a host processor or DMA controller.

These Host Interfaces (HI) are intended to minimize system chip count and "glue" logic in many computer

graphics and other multiprocessing applications. Each HI has its own control, status and data registers and

is treated as memory-mapped I/O by the DSP96002. Each interface has several dedicated interrupt vector

addresses and control bits to enable/disable interrupts. This minimizes the overhead associated with ser-

vicing the interface since each interrupt source has its own service routine.

The HI supports operation in a multiprocessor environment with a set of "host functions". The external de-

vice invoking these features is called the "host processor" and may be another DSP96002 processor or a

32-bit microprocessor such as the 68020, 68030, 68040 or 88000. Host processors with 32, 24 or 16-bit

data buses may access all status and control bits of the HI. Host processors with an 8-bit data bus should

add additional hardware to be able to access all status and control bits.

The HI functions allow:

•

a host processor to transfer data having an arbitrary address to/from the DSP96002 without
using external shared memory.

•

a host processor to interrupt the DSP96002 using multiple interrupt vectors without using ex-
ternal shared memory.

•

a host processor (with DMA capability) to transfer data blocks to/from the DSP96002 without
using external shared memory.

•

an external DMA controller to transfer data blocks to/from the DSP96002 without using exter-
nal shared memory.

•

unbuffered systems with minimum external logic as well as large buffered systems.

The HI connects to the external world thorough the external expansion port and a set of dedicated pins (de-

scribed in Section 2):

•

32-bit bidirectional data bus D0-D31.

•

5 control lines: R/

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—

–

—

–

—

–

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address lines A2-A5.