Motorola DSP96002 - Manual (Page 756)

D-4 DSP96002 USER’S MANUAL MOTOROLA
x
max,n
= (2 - 0.5
p-1
) 2
emax - bias
For SP this equals approximately (using the values in Table D-1) 3.4 • 10
38
.
2. Denormalized Numerical Values ( e = e
min
-1, f
≠
0 ): When the exponent e equals the value e
min
-
1 and the fraction field is non-zero the floating point number is called denormalized, and the
implicit integer bit b0 is equal to zero. The numerical value of a denormalized number y is given
by:
y = (-1)
s
• 0.f • 2
emin-bias
The denormalization of the fractional part allows the representation of very small numbers near
the underflow threshold. The smallest possible magnitude of any denormalized number equals
( f=f
min
) :
y
min
= (0.5)
p-1
• 2
emin - bias
For SP denormalized numbers, this results in a smallest magnitude of 1.4 • 10
-45
.
3. Zeros ( e = e
min
-1,f=0 ): Floating point value(s) of zero are encoded by a biased exponent e
equal to e
min
-1, and a fractional field f of all zeros. Note that this encoding retains a significant
sign bit: plus and minus zero are two separate entities. Figure D-2 shows the encoding of plus
and minus zero in floating point format.
4. Infinities (e = e
max
+ 1, f = 0) Infinities are encoded in the floating point format by a biased ex-
ponent equal to e
max
+1, and a fractional field f consisting of all zeros. The sign bit distinguishes
between + and -
∞
. Figure D-3 shows the encodings for + and -
∞
in SP and DP.
5. NaNs (e = e
max
+1, f
≠
0): NaNs are encoded in the floating point format by a biased exponent
equal to e
max
+1, and a nonzero fractional field. The value of the sign bit is irrelevant in this en-
coding.
QNaNs (b
1
=1) Quiet NaNs are represented by a fraction with MSB = 1 (and e=e
max
+1). The DSP96002 only
fully supports one QNaN, as required by the standard. This QNaN is encoded by a fractional field of all ones
( all b
i
= 1 in f) ("legal" QNaN). Other types of QNaNs ("illegal" NaNs) may occur in multiprocessing situa-
tions (as generated by other processors) however, and do deliver well-defined results in the DSP96002.
When QNaNs other than the "legal" QNaN occur as operand(s) to floating point arithmetic, the delivered
result is always a "legal" QNaN. Figure D-4 shows the encoding for QNaNs.
SNaNs (b
1
=0) Signaling NaNs are never generated by the DSP96002 as arithmetic results, but may appear
in the DSP96002 memory as passed along by other processors. SNaNs are characterized by a MSB of the
fractional field equal to 0 (and e = e
max
). When a SNaN appears as an operand of an arithmetic instruction,
the invalid operation exception is signaled, and the result is returned as a "legal" QNaN.
The two basic formats, discussed in the previous paragraphs, are the only formats which are used for rep-
resentation of floating point values in the DSP96002 memory (internal and/or external). As is shown in Ap-
pendix D.1.4, the SEP format, generated exclusively by the data ALU as a result of floating point arithmetic
operations, is embedded in the DP format, and is thus stored implicitly as a DP number with zeros in the
lower 21 bits of the fraction.