Motorola DSP96002 - Manual (Page 334)

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FMPY//FSUB.S Floating-Point FMPY//FSUB.S
Multiply and Subtract
Operation:
S1 * S2
→
ROUND(MP)
→
D1
(parallel data bus move)
D2 - S3
→
ROUND(SP)
→
D2
Assembler Syntax:
FMPY S1,S2,D1 FSUB.S S3,D2
(move syntax - see the MOVE instruction descrip-
tion.)
FMPY S2,S1,D1 FSUB.S S3,D2
(move syntax - see the MOVE instruction descrip-
tion.)
Description:
Multiply the two operands S1 and S2, round to the precision indicated by the MP mode bit and store the
result in the specified destination register D1. Simultaneously, subtract S3 from D2, round to single pre-
cision and store the result in the destination operand D2. Typically, if the result of the multiplication will be
used immediately following FADD (i.e., equivalent to an FMAC), the maximum precision (MP=1) will be
programmed. For the special case of |s|=|D|, the result can be +0 or -0; the sign of the resulting zero will
be the sign of the input operand in D.
Input Operand(s) Precision: SEP Floating-Point.
Subtraction Output Operand Precision: SP Floating-Point.
Multiplication Output Operand Precision: as indicated by MP.
CCR Condition Codes:
C - Not affected.
V - Not affected.
Z - Set if result of the subtraction is zero. Cleared otherwise.
N - Set if result of the subtraction is negative. Cleared otherwise.
I - Set if result of the subtraction is infinity. Cleared otherwise.
LR - Not affected.
–
R - Not affected.
A - Not affected.
ER Status Bits:
INX -Set if the result of the subtraction or multiplication is inexact. Cleared otherwise.
DZ -Always cleared.
UNF -Set if the result of the subtraction or multiplication underflows. Cleared otherwise.
OVF -Set if the result of the subtraction or multiplication overflows. Cleared otherwise.