Motorola DSP96002 - Manual (Page 24)

MOTOROLA DSP96002 USER’S MANUAL 3 - 1
SECTION 3
CHIP ARCHITECTURE
3.1 INTRODUCTION
The DSP96002 architecture is a 32-bit highly-parallel multiple-bus IEEE floating-point processor. The ar-
chitecture is designed to accommodate various IC family members with different memory and on-chip pe-
ripheral requirements while maintaining a standard programmable core. The overall chip architecture is
presented and detailed block diagrams of the Data ALU and Address Generation Unit AGU) core architec-
ture are described.
3.2 DSP96002 BLOCK DIAGRAM
The major components of the DSP96002 are
• Data Buses
• Address Buses
• Data ALU
• Address Generation Unit
• X Data Memory
• Y Data Memory
• Program Control and System Stack
• Program Memory
• Port A and Port B External Bus Interfaces
• Internal Bus Switch and Bit Manipulation Unit
• I/O Interfaces
An overall block diagram of the DSP96002 architecture is shown in Figure 3-1.
3.2.1 Data Buses
Data movement on the chip occurs over five bidirectional 32-bit buses, X Data Bus (XDB), Y Data Bus
(YDB), Global Data Bus (GDB), the DMA Data Bus (DDB) and the Program Data Bus (PDB). The X and Y
data buses may also be treated by certain instructions as one 64-bit data bus by concatenation of XDB and
YDB. Data transfer between the Data ALU and the X Data Memory and Y Data Memory occur over the X
Data Bus and Y Data Bus. These are kept local on the chip to maximize speed and minimize power. The
direct memory access data transfers occur over the DMA Data Bus. Program memory data transfers and
instruction fetches occur over the Program Data Bus. All other data transfers occur over the Global Data
Bus.