Motorola DSP96002 User Manual

Page 111

MOTOROLA

DSP96002 USER’S MANUAL

7 - 25

TXDE may be used to assert the Host Request

—

–

R pin if the Transmit Request Enable bit (TREQ) is set.

TXDE provides valid status regardless of whether the TXDE interrupt is enabled or not so that polling tech-

niques may be used by the host processor.

7.4.13.3

ICS Transmitter Ready (TRDY) Bit 2

The read-only Transmitter Ready (TRDY) status bit indicates that both the Transmit Register TX (on the

host processor side) and Host Receive Data Register HRX (on the DSP96002 side) are empty. TRDY may

be used to assert the Host Request

—

–

R pin if the Transmitter Ready Request Enable bit (TYEQ) is set.

TRDY provides valid status regardless of whether the TRDY interrupt is enabled or not so that polling tech-

niques may be used by the host processor. TRDY is set by INIT (TREQ=1), HOST reset, and HW/SW reset.

7.4.13.4

ICS Receive Request Enable (RREQ) Bit 3

RREQ is used to enable host processor interrupts/requests via the external Host Request

—

–

R pin when

the Receive Data Register Full (RXDF) status bit is set. When RREQ is cleared, RXDF interrupts are dis-

abled. When RREQ is set, the Host Request

—

–

R pin will be asserted if RXDF is set.

In DMA Mode (DMAE=1), RREQ must be set or cleared by software to select the direction of DMA transfers.

Setting RREQ defines the direction of DMA transfer to be DSP96002

→

external DMA, and enables the

—

–

R pin to request these data transfers.

See Figure 7-15 and Figure 7-16 for a summary of the effect of RREQ on the

—

–

R pin. RREQ is cleared

by HW/SW reset.

7.4.13.5

ICS Transmit Request Enable (TREQ) Bit 4

TREQ is used to enable host processor interrupt/requests via the Host Request

—

–

R pin when the Trans-

mit Data Register Empty (TXDE) status bit is set. When TREQ is cleared, TXDE interrupts are disabled.

When TREQ is set, the Host Request

—

–

R pin will be asserted if TXDE is set.