Motorola DSP96002 - Manual (Page 210)

A - 22 DSP96002 USER’S MANUAL MOTOROLA
AND Logical AND AND
(u u)
D d d d
Dn.L n n n where nnn = 0-7
S s s s
Dn.L n n n where nnn = 0-7
Timing: 2 + mv oscillator clock cycles
Memory: 1 + mv program words
DATA BUS MOVE FIELD 00 0sss uu00 1ddd
31 14 13 0
OPTIONAL EFFECTIVE ADDRESS EXTENSION OR IMMEDIATE LONG DATA
Operation:
D.L & S.L
→
D.L (parallel data bus move)
Assembler Syntax:
AND S,D (move syntax - see the MOVE instruc-
tion description.)
Description:
Logically AND the low portion of the two specified operands and store the result in the low portion of D.
Input Operand(s) Precision: 32-bit integer.
Output Operand Precision: 32-bit integer.
CCR Condition Codes:
C - Not affected.
V - Always cleared.
Z - Set if result is zero. Cleared otherwise.
N - Set if result is negative. Cleared otherwise.
I - Not affected.
LR - Not affected.
–
R - Not affected.
A - Not affected.
ER Status Bits: Not affected.
IER Flags: Not affected.
Instruction Format: AND S,D (move syntax - see the MOVE instruction description.)
Instruction Fields: