Motorola DSP96002 - Manual (Page 262)

A - 74 DSP96002 USER’S MANUAL MOTOROLA
DO Start Hardware Loop DO
Operation:
LA
→
SSH; LC
→
SSL; X:
→
LC
PC
→
SSH; SR
→
SSL; expr
→
LA; 1
→
LF
LA
→
SSH; LC
→
SSL; Y:
→
LC
PC
→
SSH; SR
→
SSL; expr
→
LA; 1
→
LF
LA
→
SSH; LC
→
SSL; S
→
LC
PC
→
SSH; SR
→
SSL; expr
→
LA; 1
→
LF
LA
→
SSH; LC
→
SSL; #xxx
→
LC
PC
→
SSH; SR
→
SSL; expr
→
LA; 1
→
LF
Assembler Syntax:
DO X: ea, label
DO Y: ea, label
DO S,label
DO #count,label
Description:
Begin a hardware DO loop that is to be repeated the number of times specified in the instruction’s source
operand and whose range of execution is terminated by the destination operand (previously shown as "ex-
pr"). No overhead other than the execution of this DO instruction is required to set up this loop. DO loops
can be nested and the loop count can be passed as a parameter.
During the first instruction cycle, the current contents of the loop address (LA) and the loop counter (LC)
registers are pushed onto the system stack. The DO instruction’s source operand is then loaded into the
loop counter (LC) register. The LC register contains the remaining number of times the DO loop will be ex-
ecuted and can be accessed from inside the DO loop subject to certain restrictions. If LC equals zero, the
DO loop is executed 2
32
times. All address register indirect addressing modes (less long displacement) may
be used to generate the effective address of the source operand. Register Direct addressing mode may also
be used. If immediate short data is specified, the LC is loaded with the zero extended 19-bit immediate
data.
During the second instruction cycle, the current contents of the program counter (PC) register and the status
register (SR) are pushed onto the system stack. The stacking of the LA, LC, PC, and SR registers is the
mechanism which permits nesting DO loops. The DO instruction’s 32-bit absolute address extension word
(which is the destination operand and shown as "expr") is then loaded into the loop address (LA) register.
The value in the program counter (PC) register pushed onto the system stack is the address of the first in-
struction following the DO instruction (i.e., the first actual instruction in the DO loop). This value is read
(i.e., copied but not pulled) from the top of the system stack to return to the top of the loop for another pass
through the loop.
During the third instruction cycle, the loop flag (LF) is set. This results in the PC being repeatedly compared
with LA to determine if the last instruction in the loop has been fetched. If LA equals PC, the last instruction
in the loop has been fetched and the loop counter (LC) is tested. If LC is not equal to one, it is decremented
by one and SSH is loaded into the PC to fetch the first instruction in the loop again. If LC equals one, the