Motorola DSP96002 - Manual (Page 313)

MOTOROLA DSP96002 USER’S MANUAL A - 125
FJScc Floating-Point Jump To Subroutine FJScc
Conditionally
Operation:
If cc, then PC
→
SSH; SR
→
SSL; xx
→
PC
else PC+1
→
PC
If cc, then PC
→
SSH; SR
→
SSL; ea
→
PC
else PC+1
→
PC
Assembler Syntax:
FJScc label (short)
Description:
If the specified floating-point condition is true, the address of the instruction immediately following the
FJScc instruction and the status register are pushed onto the stack. Program execution then continues at
the effective address in program memory. If the specified condition is false, the PC is incremented and
any extension word is ignored. However, the address register specified in the effective address field is
always updated independently of the condition. All memory alterable addressing modes may be used for
the effective address. A fast Short Jump addressing mode may also be used. The 15-bit data is sign ex-
tended to form the effective address. See Section A.10 for restrictions. Non-aware floating-point condi-
tions set the SIOP flag in the IER and the UNCC bit in the ER if the NAN bit is set. This action occurs before
stacking the status register when the specified non-aware floating-point condition is true.
"cc" may specify the following conditions:
Non-aware
Mnemonic Condition Set UNCC*
EQ - equal Z = 1 No
ERR - error UNCC v SNAN v OPERR v No
OVF v UNF v DZ = 1
GE - greater than or equal NAN v (N & ~Z) = 0 Yes
GL - greater or less than NAN v Z = 0 Yes
GLE - greater, less or equal NAN = 0 Yes
GT - greater than NAN v Z v N = 0 Yes
INF - infinity I = 1 Yes
LE - less than or equal NAN v ~(N v Z) = 0 Yes
LT - less than NAN v Z v ~N = 0 Yes
MI - minus N = 1 No
NE(Q) - not equal Z = 0 No
NGE - not(greater than or equal) NAN v (N & ~Z) = 1 Yes
NGL - not(greater or less than) NAN v Z = 1 Yes
NGLE - not(greater, less or equal) NAN = 1 Yes
NGT - not greater than NAN v Z v N = 1 Yes
NINF - not infinity I = 0 Yes
NLE - not(less than or equal) NAN v ~(N v Z) = 1 Yes
NLT - not less than NAN v Z v ~N = 1 Yes
OR - ordered NAN = 0 No
PL - plus N = 0 No
UN - unordered NAN = 1 No
Note: The operands for the ERR condition are taken from the ER register.
* See the description of the UNcc bit in Section A.4.
CCR Condition Codes: Not affected.