Motorola DSP96002 - Manual (Page 43)

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ister will be accessed for an address register update calculation involving an address register of the same
number (i.e., M0 is accessed when R0 is to be updated, M1 for R1, etc.). Each modifier register is set to
$FFFFFFFF on processor reset which specifies the default value for linear arithmetic register update calcu-
lations.
4.6 PROGRAM COUNTER (PC)
This 32-bit register contains the address of the next location to be fetched from Program Memory Space.
The PC may point to instructions, data operands or addresses of operands. References to this register are
always inherent and are implied by most instructions. This special purpose address register is stacked when
program looping is initiated, jump to subroutine is performed, and when interrupts occur except for fast in-
terrupts (refer to Section 8.3).
4.7 STATUS REGISTER (SR)
The SR is a 32-bit register consisting of an 8-bit Mode register (MR), an 8-bit IEEE Exception register (IER),
an 8-bit Exception register (ER) and an 8-bit Condition Code register (CCR).
The MR bits are only affected by processor reset, exception processing, the DO, DOR, ENDDO, ILLEGAL,
RTI, RTR, FTRAPcc and TRAPcc instructions and by instructions which directly reference the MR register.
The IER bits are affected by processor reset, by instructions which directly reference the IER register and
by the Data ALU floating-point operations. The IER contains the IEEE Rounding Mode control and the five
exceptions flags as defined by the IEEE 754 standard. The five exception flags are "sticky" and the only way
in which they can be cleared is by hardware reset or by the user writing the IER register. The purpose of
making bits sticky is to prevent them from accidentally being cleared before being processed or used later
by other instructions. The standard definition of the IER bits and the complete IER exception flag computa-
tion rules are given in Section A.5. It is strongly recommended that users of the DSP96002 obtain and com-
prehend the ANSI/IEEE Standard 754-1985 so that the full advantage of the standard can be realized.
The ER bits are affected by processor reset, by instructions which directly reference the ER register and by
the Data ALU floating-point operations. The ER reflects the exceptions produced as a result of the execution
of the last instruction. The standard definition of the ER bits and the complete ER bit computation rules are
given in Section A.4.
The CCR contains flags that reflect the status produced by Data ALU instructions currently executing. The
CCR bits are affected by Data ALU operations and by instructions which directly reference the CCR register.
The standard definition of the CCR bits and the complete CCR bit computation rules are given in Section
A.3.
The SR register is stacked when program looping is initialized, jump or branch to subroutine is performed,
and when interrupts occur except for fast interrupts (refer to Section 8). The SR format is shown in Figure
4-3, and is described below.
4.7.1 CCR Carry (C) Bit 0
The carry bit is set if a carry is generated in an integer addition or if a borrow is generated in an integer
subtraction. The carry bit is also modified by bit manipulation, rotate, and shift integer instructions as well
as by the Address Generation Unit operation when executing MOVETA instructions. The carry bit is not af-
fected by floating-point instructions. The C bit is cleared during processor reset.