Motorola DSP96002 - Manual (Page 328)

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FMPY//FADD.X Floating-Point FMPY//FADD.X
Multiply and Add
Description:
Multiply the two operands S1 and S2, round to single extended precision and store the result in the spec-
ified destination register D1. Simultaneously, add the two operands S3 and D2, round to single extended
precision and store the result in the destination operand D2.
Input Operand(s) Precision: SEP Floating-Point.
Addition Output Operand Precision: SEP Floating-Point.
Multiplication Output Operand Precision: SEP Floating-Point.
CCR Condition Codes:
C - Not affected.
V - Not affected.
Z - Set if result of the addition is zero. Cleared otherwise.
N - Set if result of the addition is negative. Cleared otherwise.
I - Set if result of the addition is infinity. Cleared otherwise.
LR - Not affected.
–
R - Not affected.
A - Not affected.
ER Status Bits:
INX -Set if the result of the addition or the multiplication is inexact. Cleared otherwise.
DZ -Always cleared.
UNF -Set if the result of the addition or the multiplication underflows. Cleared otherwise.
OVF -Set if the result of the addition or the multiplication overflows. Cleared otherwise.
OPERR-Set if one of the multiply operands is infinity and the other is zero. Set if the addition
operands are opposite-signed infinities. Cleared otherwise.
SNAN -Set if anyone of the source operands is a signaling NaN. Cleared otherwise.
NAN -Set if result of the addition is a NaN. Cleared otherwise.
UNCC -Always cleared.
Assembler Syntax:
FMPY S1,S2,D1 FADD.X S3,D2
(move syntax - see the MOVE instruction descrip-
tion.)
FMPY S2,S1,D1 FADD.X S3,D2
(move syntax - see the MOVE instruction descrip-
tion.)
Operation:
S1 * S2
→
ROUND(SEP)
→
D1
(parallel data bus move)
S3 + D2
→
ROUND(SEP)
→
D2