Motorola DSP96002 - Manual (Page 182)

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10.9.1 PAB Register for Fetch (OPABFR)
The PAB Register for Fetch is a 32-bit register that stores the address of the last instruction that was fetched
before the Debug Mode was entered. OPABFR can only be read through the serial interface. This register
is not affected by the operations performed during the Debug Mode.
10.9.2 PAB Register for Decode (OPABDR)
The PAB Register for Decode is a 32-bit register that stores the address of the instruction currently in the
Instruction Latch. This is the instruction that would have been decoded if the chip would not have entered
the Debug Mode. OPABDR can only be read through the serial interface. This register is not affected by the
operations performed during the Debug Mode.
10.9.3 PAB FIFO
To ease the debugging activity and keep track of the program flow, a First-In-First-Out buffer is provided
which stores the addresses of the last five instructions that were executed. The FIFO is implemented as a
circular buffer containing five 32-bit registers and one 3-bit counter. All the registers have the same address
but any read access to the FIFO address will cause the counter to increment thus pointing to the next FIFO
register. The registers are serially available to the command controller through their common FIFO address.
Figure 10-8 illustrates a block diagram of the Program Address Bus FIFO. The FIFO is not affected by the
operations performed during the Debug Mode except for the FIFO pointer increment when reading the
FIFO. The last instruction executed before entering debug mode will be on the bottom of the FIFO.
Caution
To ensure FIFO coherence, a complete set of five reads of the FIFO must be per-
formed. This is necessary due to the fact that each read increments the FIFO pointer
thus pointing to the next location. After five reads the pointer will point to the same
location as before starting the read procedure.
10.10 SERIAL PROTOCOL DESCRIPTION
In order to permit an efficient means of communication between the command controller and the DSP96002
chip, the following protocol is adopted. Before starting any debugging activity the command controller has
to wait for an acknowledge that the chip has entered the Debug Mode. Note that in case of a breakpoint,
trace, or software (F)DEBUGcc instruction, the acknowledge itself is the initiates the debug session. The
command controller communicates with the chip by sending 8-bit commands that may be accompanied by
32-bit data. After sending a command the command processor waits for the chip to acknowledge execution
of the command. The command processor may send a new command only after the chip has acknowledged
execution of the previous command.
10.10.1 OnCE

Commands
There are two types of commands: read commands (when the chip will deliver required data) and write com-
mands (when the chip will receive data and will write the data in one of the on-chip resources). The com-
mands are 8 bits long and have the format shown in Figure 10-9.
10.10.1.1 Register Select (RS4-RS0) Bits 0-4
The Register Select bits define which register is source(destination) for the read(write) operation.