Motorola DSP96002 User Manual

Page 8

MOTOROLA

DSP96002 USER’S MANUAL

2 - 5

Bus Control VCC(2)

(Power) - isolated power for the bus control I/O drivers. Must be tied to all other

chip power pins externally. User must provide adequate external decoupling capacitors.

Bus Control VSS(4)

(Ground) - isolated ground for the bus control I/O drivers. Must be tied to all oth-

er chip ground pins externally. User must provide adequate external decoupling capac-

itors.

2.1.4 On-chip Emulator Interface (OnCE) (4 Pins)

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(Debug Request) - The debug enable input provides a means of entering the debug

mode of operation from the external command controller. This pin when asserted causes

the DSP96002 to finish the current instruction being executed, save the instruction pipe-

line information, enter the debug mode and wait for commands to be entered from the

debug serial input line.

DSCK/OS1

(Debug Serial Clock/Chip Status 1) - The DSCK/OS1 pin, when configured as an input,

is the pin through which the serial clock is supplied to the OnCE. The serial clock pro-

vides pulses required to shift data into and out of the OnCE serial port. When output (not

in Debug Mode), this pin in conjunction with the OS0 pin, provides information about the

chip status.

DSI/OS0

(Debug Serial Input/Chip Status 0) - The DSI/OS0 pin, when configured as an input, is

the pin through which serial data or commands are provided to the OnCE controller. The

data received on the DSI pin will be recognized only when the DSP 96002 has entered

the debug mode of operation. When configured as an output (not in Debug Mode), this

pin in conjunction with the OS1 pin, provides information about the chip status.

DSO

(Debug Serial Output)

The debug serial output provides the data contained in one of the

OnCE controller registers as specified by the last command received from the external

command controller. When a trace or breakpoint occurs this line will be asserted for one

T cycle to indicate that the chip has entered the debug mode and is waiting for com-

mands.

2.1.5 Port A and Port B (162 Pins)

Port A and Port B are identical in pinout and function. The following pin descriptions apply to both ports.

Each port may be a bus master and each port has a host interface which can be accessed on demand.

The pins are specified for a 50 pf load and two external TTL loads. Derating curves will be provided spec-

ifying performance up to 250 pf capacitive loads.

A0-A31

(Address Bus) - three-state, active high outputs when a bus master. When not a bus

master, A2-A5 are active high inputs, A0-A1 and A6-A31 are three-stated. As inputs,

A2-A5 may change asynchronous relative to the input clock (CLK). A2-A5 are host in-

terface address inputs which are used to select the host interface register. When a bus

master, A0-A31 specify the address for external program and data memory accesses.

If there is no external bus activity, A0-A31 remain at their previous values. When a bus

master, the Address Enable (

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E) input acts as an output enable control for A0-A31.

When a bus master, A0-A31 are stable whenever the transfer strobe

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S is asserted