Clr clear an operand clr – Motorola DSP96002 User Manual
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DSP96002 USER’S MANUAL
MOTOROLA
CLR
Clear an Operand
CLR
Instruction Fields:
(u u u)
D
d d d
Dn.L
n n n
where nnn = 0-7
Timing: 2 + mv oscillator clock cycles
Memory: 1 + mv program words
11
0uuu
1000
1ddd
31
14 13
0
OPTIONAL EFFECTIVE ADDRESS EXTENSION OR IMMEDIATE LONG DATA
DATA BUS MOVE FIELD
Operation:
0
→
D.L (parallel data bus move)
Assembler Syntax:
CLR D (move syntax - see the MOVE instruction
description.)
Description:
The low portion of the destination operand is cleared to zero. This instruction is implemented by executing
ANDC D,D.
Input Operand(s) Precision: 32-bit integer.
Output Operand Precision: 32-bit integer.
CCR Condition Codes:
C
- Not affected.
V
- Always cleared.
Z
- Always set.
N
- Always cleared.
I
- Not affected.
LR
- Not affected.
–
R
- Not affected.
A
- Not affected.
ER Status Bits: Not affected.
IER Flags: Not affected.
Instruction Format: CLR D (move syntax - see the MOVE instruction description.)