Motorola DSP96002 - Manual (Page 565)

B-46 DSP96002 USER’S MANUAL MOTOROLA
rmin equ -3.14159
range equ 2*3.14159
o_range equ 1.0/range
Program ICycles
Words
move #range,d7.s ;load desired range
move #rmin,d2.s ;load range min
move #o_range,d3.s ;load reciprocal of range
fadd.s d2,d0 ;adjust to rmin 1 1
fmpy.s d0,d3,d0 ;scale the input 1 1
floor d0,d1 ;get integer part 1 1
fsub.s d1,d0 ;get fractional part 1 1
fmpy.s d7,d0d0 ;spread out fraction to range 1 1
fadd.s d2,d0 ;adjust to rmin 1 1
--- ---
Totals: 6 6
The output is in d0. Note that the constant initialization is not included in the benchmark because it does
not need to be executed every time argument reduction is desired and is therefore application dependent.
If the desired range begins at zero (i.e. the desired range is zero to two pi), then the first and last fadd in-
structions can be deleted for a four cycle argument reduction.
This is one possible method for AR and it is efficient. This method will not work when the argument divided
by the result range has no fractional part (in the current precision). This is obvious since it is the fractional
part that contains the information relating to how far the scaled argument is in the reduced range. The in-
teger part tells how many times the range has wrapped around. Typically, a good programmer will keep
the argument to a few multiples of the desired range. In most practical applications, the argument may ex-
ceed the desired range by several integral values. In this case, the presented algorithms work very well.
After the final reduced argument has been obtained, any increments should be made from the reduced ar-
gument to prevent eventual overflow and maintain maximum precision.
B.1.26 Non-IEEE floating-point Division
The following code segments perform the division of d0/d5. The resulting quotient is in d0. These code
segments are used for a fast division without the need to conform to the error checking or error bounds of
the IEEE standard.
The code uses a "convergent division" algorithm. The initial seed obtained from the FSEEDD instruction
has 8 bits of accuracy. Two iterations of the convergent division algorithm provide approximately 32 bits
of accuracy. For more information on the convergent division algorithm, consult "Computer Arithmetic,
Principles, Architecture, and Design" by Kai Hwang, 1979, John Wiley and Sons, New York.
Non-IEEE Division Algorithm