Motorola DSP96002 User Manual

Page 115

MOTOROLA

DSP96002 USER’S MANUAL

7 - 29

es. In this mode, the

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R pin can be used as an interrupt request to the host processor, and the

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pin may be used to support a 68K family interrupt acknowledge.

When DMAE is set, the HI operates in the DMA Mode. When in DMA Mode, the RX and TX registers are

accessed without regard to the address lines A2-A5, permitting data transfers under control of external de-

vices, such as DMA controllers, that do not supply addresses. The

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–

R pin is used as a DMA transfer

request to the external DMA controller. The direction of the DMA transfer is selected by TREQ and RREQ.

Bidirectional DMA transfers are not supported; the user cannot set both RREQ and TREQ in the DMA mode.

Also, TYEQ should remain cleared.

7.4.13.14

ICS Host Reset Status (HRST) Bit 13

The read-only Host Reset Status bit (HRST) may be tested by the host processor to verify the state of the

HRES control bit. If HRST is set, the HRES bit is set and the HI is in the reset state. If the HRST bit is

cleared, the HRES bit is cleared and the HI operation is enabled. The HRST bit is cleared by clearing HRES.

The HRST bit is set by HOST reset and HW/SW reset.

7.4.13.15

ICS Reserved bits (Bits 14, 16-31)

Reserved bits are read by the host processor as zero. They should be written with zero for future compati-

bility.

7.4.13.16

ICS Host Memory Read Command (HMRC) Bit 15

The read-only Host Memory Read Command status bit (HMRC) may be tested by the host processor to ver-

ify when data written to the HTXC register (96002 side) is transferred to the RX register (host processor

side).

HMRC is set when the host processor writes into the TX register using the host function "TX register write

and X/Y/P Memory Read Interrupt". HMRC is cleared when the HTX register contents which were written,

in the DSP96002 side, thorough the HTXC address, are transferred to the RX register in the host processor

side. HMRC is cleared by INIT (TREQ=1), HOST reset, and HW/SW reset.

7.4.14

Semaphore Register (SEM) - Host Processor Side

The Semaphore Register (SEM) is a 32-bit read/write register used by the host processor to control the HI

allocation in a multiprocessor system and show the current host processor ID.

7.4.14.1

SEM Host Semaphore (SEM0-SEM15) Bits 0-15

The Host Semaphore register bits SEM0-SEM15 are used by host processors for software arbitration of

mastership over the HI. This register does not affect the HI operation and only serves as a read/write sema-

phore repository. All external host processors that compete for mastership over the HI should work accord-

ing to the same software protocol for handing over the HI from one host processor to another.

Typically, a host processor, before accessing the HI, checks the Semaphore Register to see if the HI is al-

located to another host processor. If SEM0-SEM15 are not cleared then the HI is already allocated and the

host processor cannot access the HI. If SEM0-SEM15 are cleared then the HI is assumed free and the host

processor writes SEM0-SEM15. The host processor can either set just one bit (which will serve as a host