Motorola DSP96002 - Manual (Page 13)

2 - 10 DSP96002 USER’S MANUAL MOTOROLA
register (IVR) onto the data bus outputs D0-D31. This provides an interrupt acknowl-
edge capability compatible with MC68000 family processors.
If the host interface is in DMA mode,
—
H
–
A is used as a DMA transfer acknowledge in-
put and it is asserted by an external device to transfer data between the Host Interface
registers and an external device. In DMA read mode,
—
H
–
A is asserted to read the Host
Interface RX register on the data bus outputs D0-D31. In DMA write mode,
—
H
–
A is as-
serted to strobe external data into the Host Interface TX register. Write data is latched
into the TX register on the rising edge of
—
H
–
A.
—
H
–
R (Host Request) - active low output, never three-stated. The host request
—
H
–
R is as-
serted to indicate that the host interface is requesting service - either an interrupt request
or a DMA request - from an external device.
The
—
H
–
R output may be connected to interrupt request input
—
I
—
R
—
Q
–
A,
—
I
—
R
—
Q
–
B, or
—
I
—
R
—
Q
–
C of another DSP96002. The DSP96002 on-chip DMA Controller
channel can select the interrupt request input as a DMA transfer request input.
—
B
–
R (Bus Request) - active low output, never three-stated.
—
B
–
R is asserted when the CPU
or DMA is requesting bus mastership.
—
B
–
R is deasserted when the CPU or DMA no
longer needs the bus.
—
B
–
R may be asserted or deasserted independent of whether
the DSP96002 is a bus master or a bus slave. Bus "parking" allows
—
B
–
R to be
deasserted even though the DSP96002 is the bus master. See the description of bus
"parking" in the
—
B
–
A pin description. The RH bit in the Bus Control Register (see
Section seven) allows
—
B
–
R to be asserted under software control even though the
CPU or DMA does not need the bus.
—
B
–
R is typically sent to an external bus arbitrator
which controls the priority, parking and tenure of each DSP96002 on the same external
bus.
—
B
–
R is only affected by CPU or DMA requests for the external bus, never for the
internal bus. During hardware reset,
—
B
–
R is deasserted and the arbitration is reset
to the bus slave state.
—
B
–
G (Bus Grant) – active low input.
—
B
–
G must be asserted/ deasserted synchronous to the
input clock (CLK) for proper operation.
—
B
–
G is asserted by an external bus arbitration
circuit when the DSP96002 may become the next bus master. When
—
B
–
G is asserted,
the DSP96002 must wait until
—
B
–
B is deasserted before taking bus mastership. When
—
B
–
G is deasserted, bus mastership is typically given up at the end of the current bus
cycle. This may occur in the middle of an instruction which requires more than one ex-
ternal bus cycle for execution. Note that indivisible read-modify-write instructions