Motorola DSP96002 - Manual (Page 110)

7 - 24 DSP96002 USER’S MANUAL MOTOROLA
that the host processor can force any of the existing exception handlers (IRQA, IRQB, etc.) and can use any
of the reserved or otherwise unused starting addresses provided they have been pre-programmed in the
DSP96002. The HV is set to a predefined value for each port by HW/SW reset (see Figure 7-7). If HC is set,
the host processor should not change HV.
7.4.12.2 CVR Reserved bits (Bits 8-14, 16-31)
Reserved bits are read by the host processor as zeros. They should be written with zero for future compat-
ibility.
7.4.12.3 CVR Host Command (HC) Bit 15
The Host Command bit (HC) is used by the host processor to start execution of Host Command exceptions.
Normally the host processor sets HC to request a Host Command exception service from the DSP96002.
Setting HC causes HCP (Host Command Pending) to be set in the HSR register. When the Host Command
second vector location is fetched, the HC bit is cleared by the HI hardware (interrupt acknowledge). HC is
cleared by HW/SW reset.
CAUTION:
The host processor should verify that HC is cleared before attempting to set HC. This
is necessary to avoid hardware contention between the host processor set operation
and the Host Interface clear operation when receiving the interrupt acknowledge. HC
should not be cleared by the host processor.
7.4.13 Interrupt Control/Status Register (ICS) - Host Processor Side
The Interrupt Control/Status Register (ICS) is a 32-bit read/write control and status register used by the host
processor to control the HI and verify the current status of the HI. ICS is a read/write register which can be
accessed using bit manipulation instructions. The control and status bits are described in the following para-
graphs.
7.4.13.1 ICS Receive Data Register Full (RXDF) Bit 0
The read-only Receive Data Register Full (RXDF) bit indicates that the Receive Register RX contains data
from the DSP96002 and may be read by the host processor. RXDF is set when the Host Transmit Data Reg-
ister HTX or HTXC is transferred to the Receive Register RX. RXDF is cleared when RX is read by the host
processor. RXDF is cleared by INIT (RREQ=1), HOST reset, and HW/SW reset.
RXDF may be used to assert the Host Request
—
H
–
R pin if the Receive Request Enable bit (RREQ) is set.
RXDF provides valid status regardless of whether the RXDF interrupt is enabled or not so that polling tech-
niques may be used by the host processor.
7.4.13.2 ICS Transmit Data Register Empty (TXDE) Bit 1
The read-only Transmit Data Register Empty (TXDE) bit indicates that the Transmit Register TX is empty
and can be written by the host processor. TXDE is set when the Transmit Register TX is transferred to the
Host Receive Data Register (HRX). TXDE is cleared when TX is written by the host processor. TXDE is set
by INIT (TREQ=1), HOST reset, and HW/SW reset.