Motorola DSP96002 - Manual (Page 113)

MOTOROLA DSP96002 USER’S MANUAL 7 - 27
2. When not using the
—
H
–
R pin for handshake, use polling of the INIT bit in ICS to make sure
it is cleared by the hardware (which means the INIT execution is completed). Then, start writ-
ing/reading data.
3. If using neither the
—
H
–
R pin for handshake nor polling the INIT bit, wait at least 3Tc+Th after
the deassertion of
—
T
–
S that wrote ICS, before writing/reading data. This ensures that the
INIT is completed. See Figure 7-14.
The type of initialization done depends on the state of TREQ and RREQ. If both TREQ and RREQ are
cleared, the INIT procedure will not affect the HI. The effect of the initialization procedure is described in
Figure 7-7 and Figure 7-8. The INIT bit is cleared by HW/SW reset.
CAUTION:
The host processor should verify that INIT is cleared before attempting to set INIT.
This is necessary to avoid hardware contention between the host processor set opera-
tion and the Host Interface clear operation at the end of the INIT procedure. INIT
should not be cleared by the host processor.
7.4.13.8 ICS Host Request (HREQ) Bit 7
The read-only Host Request (HREQ) bit indicates the status of the Host Request
—
H
–
R pin.
In interrupt mode (DMAE=0):
When the HREQ status bit is cleared, it indicates that the
—
H
–
R pin is deasserted and host processor in-
terrupts are not being requested. When the HREQ status bit is set, it indicates that the
—
H
–
R pin is asserted
indicating that the DSP96002 is interrupting the host processor. The HREQ interrupt request may originate
from one or more of 3 sources, selected by their enable bits RREQ, TREQ and TYEQ (See Figure 7-15):
• the RX register or HTX register is full,
• the TX register or HRX register is empty,
• both the TX register (on the host processor side) and the HRX register (on the DSP96002 side)
are empty.
In DMA Mode (DMAE=1):
When the HREQ status bit is cleared, it indicates that the
—
H
–
R pin is deasserted and no DMA transfers
are being requested. When the HREQ status bit is set, it indicates that the
—
H
–
R pin is asserted and a DMA
transfer request is being made. The DMA transfer request may originate because the Receive Register (RX)
is full when the DMA transfer direction is DSP96002
→
external DMA, or because the Transmit Register
(TX) is empty when the DMA transfer direction is external DMA
→
DSP96002 (See Figure 7-16).
The condition of RX full and TX empty is indicated by the ICS register RXDF and TXDE status bits, respec-
tively. If the interrupt source has been enabled by the associated request enable bit in the Interrupt Control
Register ICS, HREQ will be set if one or more of the 2 enabled interrupt sources is set. HREQ is cleared by
HW/SW reset. HREQ is cleared by HOST reset if both TYEQ and TREQ are cleared, and set otherwise. For
the effect of INIT on HREQ, see Figure 7-7.