Motorola DSP96002 - Manual (Page 794)

12 MOTOROLA
The PFLUSH instruction is not performed automatically when switching from cache mode
to PRAM mode to give the user full control of the cache.
2.7 SECTOR REPLACEMENT POLICY
When a sector miss occurs, a cache sector must be selected to contain the new desired
memory sector. The selected cache sector typically contains another memory sector. The
sector replacement policy determines which sector would be flushed from the cache, and
thus frees the cache sector for the new memory sector. In order to determine which sector
should be replaced during a sector miss, the SRU constantly monitors the use of request-
ed addresses and sectors and uses the information as input to the sector replacement al-
gorithm.
The sector replacement policy dictates the replacement of the Least Recently Used (LRU)
sector.
The LRU stack status is effected only in cache mode by fetch operations and by PLOCK
and PUNLOCK instructions. Locked cache sectors continue to “move” up and down the
LRU stack. This implies that when picking the least recently used sector (the one at the
bottom of the LRU stack), locked sectors that can’t be flushed from the cache should be
skipped.
When the processor is in cache mode, MOVEM instructions do not affect the LRU stack
status. When the processor is in PRAM mode, fetches, MOVEM instructions, or DMA
transfers do not effect the LRU stack status either.
2.8 DMA TRANSFERS TO/FROM PROGRAM MEMORY
DMA transfers to and from the program memory space (internal and external) are only
possible while the cache is in PRAM mode because, while the processor is in cache
mode, cache misses update the internal program memory using the DMA time slot.
Therefore, DMA transfers to/from program memory are disabled in hardware by blocking
the DMA strobes so that such DMA sequences will run without actually accessing the pro-
gram memory.
While the processor is in PRAM mode a DMA move into the internal PRAM should set the
corresponding valid-bit to indicate that the location has been initialized. This feature could
be useful is the user wishes to load the cache while the processor is still in PRAM mode.
Note that transferring code from external program memory addresses higher than 1K to
internal program memory address (0 to 1K), and then switching into cache mode would
cause non-consistency because the cache content for the first 1K addresses is different
from the external program memory for these addresses. Since the DMA transfer into in-
ternal program memory is usually used for time critical routines and interrupt vectors, and