Motorola DSP96002 - Manual (Page 759)

MOTOROLA DSP96002 USER’S MANUAL D-7
livered result is the correct SP denormalized number.
5. Inexact: The inexact exception is signaled if the delivered result differs from what would have
been obtained with infinite-precision arithmetic. For instance, the examples of underflow shown
above deliver numerically inexact results, and thus set the inexact flag. Another example is the
case where floating point numbers are rounded up or down.
D.1.4 DSP96002 Floating Point Storage Format in the Data ALU
The data ALU is designed to accommodate mixed-precision operands in a common format. To this end, a
common DP storage format is used internal to the data ALU. SP and DP numbers from memory are auto-
matically converted to the internal format by means of a format conversion unit, the operation of which is
transparent to the user.
The bit-level DP representation internal to the ALU is illustrated in Figure D-5. The internal floating point
format is 96 bits wide and consists of the following fields:
1. Sign of the mantissa (S) bit 95.
2. SP Unnormalized tag (U) bit 94. The U-TAG is set when writing a floating-point register with a
denormalized SP number. Cleared otherwise.
3. DP Unnormalized tag (V) bit 93. The V-TAG is set when writing a floating-point register with a
denormalized DP number (denormalized SEP in the DSP96002). Cleared otherwise.
4. Unused bits (Z) bits 75 through 92 and bits 0 through 10. These bits read as zeros, and should
be written with zeros for future compatibility. They are cleared by floating-point moves and op-
erations.
5. Biased Exponent (e) bits 64 through 74. Since the internal ALU format is DP, there are 11 ex-
ponent bits, with an integer bias of 1023 ($3FF). The encodings of the exponent are identical
to the ones explained in the section on memory storage formats (Appendix D.1.2) .
6. Integer bit (i or b
0
) bit 63. The integer bit is explicitly presented in the internal representation as
bit 63 and is the integer part of the mantissa.
7. Fraction – bits 11 through 62. This is a 52-bit field representing the fractional part of the man-
tissa (only 31 are used by the DSP96002 floating-point ALU). The remaining bits are set to
zero by floating-point ALU operations or single-precision floating-point moves. Since the inter-
nal format is DP, the fraction consists of 52 bits. The data ALU arithmetic, however, only pro-
vides results in either SP or SEP. The SEP format is the same as the DP format, except for the
size of the fraction. The SEP fraction consists of only 31 bits. Consequently, the lower 21 or 29
bits of the fraction will consist of zeros when representing SEP or SP arithmetic results, respec-
tively. When DP values are moved from memory to the data ALU, the fraction contains all 52
significant bits. However, when using these DP values as operands in a floating-point arithmetic
operation, only 31 bits of the 52-bit fraction are used; the remaining bits are simply truncated.
The SEP format is shown in Figure D-7.
D.1.5 Data ALU Block Diagram
The block diagram of the data ALU is shown in Figure D-8. The data ALU consists of four main parts:
1. Register file and automatic conversion unit: All operations in the data ALU are register-based:
operands as well as results of data ALU operations are read from and written to registers. A