Motorola DSP96002 - Manual (Page 310)

A - 122 DSP96002 USER’S MANUAL MOTOROLA
FJcc Floating-Point Jump Conditionally FJcc
Operation:
If cc, then xx
→
PC
else PC+1
→
PC
If cc, then ea
→
PC
else PC+1
→
PC
Assembler Syntax:
FJcc label (short)
FJcc ea
Description:
If the specified floating-point condition is true, program execution then continues at a location specified by
an effective address in the instruction. If the specified condition is false, the PC is incremented and the
effective address is ignored. However, the address register specified in the effective address field is al-
ways updated independently of the condition. All memory alterable addressing modes may be used for
the effective address. A Fast Short Jump addressing mode may also be used. The 15-bit data is sign
extended to form the effective address. See Section A.10 for restrictions. Non-aware floating-point con-
ditions set the SIOP flag in the IER register and the UNCC bit in the ER register if the NAN bit is set.
"cc" may specify the following conditions:
Non-aware
Mnemonic Condition Set UNCC*
EQ - equal Z = 1 No
ERR - error UNCC v SNAN v OPERR v No
OVF v UNF v DZ = 1
GE - greater than or equal NAN v (N & ~Z) = 0 Yes
GL - greater or less than NAN v Z = 0 Yes
GLE - greater, less or equal NAN = 0 Yes
GT - greater than NAN v Z v N = 0 Yes
INF - infinity I = 1 Yes
LE - less than or equal NAN v ~(N v Z) = 0 Yes
LT - less than NAN v Z v ~N = 0 Yes
MI - minus N = 1 No
NE(Q) - not equal Z = 0 No
NGE - not(greater than or equal) NAN v (N & ~Z) = 1 Yes
NGL - not(greater or less than) NAN v Z = 1 Yes
NGLE - not(greater, less or equal) NAN = 1 Yes
NGT - not greater than NAN v Z v N = 1 Yes
NINF - not infinity I = 0 Yes
NLE - not(less than or equal) NAN v ~(N v Z) = 1 Yes
NLT - not less than NAN v Z v ~N = 1 Yes
OR - ordered NAN = 0 No
PL - plus N = 0 No
UN - unordered NAN = 1 No
Note: The operands for the ERR condition are taken from the ER register.
* See the description of the UNcc bit in Section A.4.